Electrostatic discharge (ESD) can result in permanent damage to an integrated circuit (IC). Most ICs operate at potentials under 25 volts, whereas ESD can greatly exceed such potentials. Damage is believed to occur when the high potential breaks down insulating barriers within the integrated circuitry, and the resulting current results in the permanent break down of the insulation. Regardless of the dynamics, it is desireable that the high potentials associated with ESD be dissipated before such damage can occur.
Prior art conventional means of providing for protection against damage due to inadvertent electrostatic discharge make use of diode and transistor clamps to shunt current away from sensitive internal circuit nodes. These devices can clamp to V.sub.SS, V.sub.CC or both. It is desirable in many applications to provide clamp devices to V.sub.SS only, to avoid excessive input current when inputs go more than a forward biased diode drop above V.sub.CC. It also allows for reduced layout area to provide clamps to one supply only. It further eliminates any NPNP SCR structures that can result in destructive latch-up if accidentally triggered by any number of means. A concern in clamping to V.sub.SS only is maintaining sufficient ESD protection when undergoing positive input ESD with respect to V.sub.SS. This condition results in reverse bias breakdown of the clamp devices which can be destructive.
In this disclosure, "n" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic, which introduce negatively charged majority carriers into the silicon, and "p" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron or phosphorus, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively.
While silicon is used in the preferred embodiment, as is known to those skilled in the art of semiconductor manufacture, the invention is applicable to other doped semiconductor material. "n" indicates an excess of "negative" carriers (electrons) floating around in the material, from high valence impurities. "p" indicates material with an excess of "positive" carriers, or "holes", caused by low valence dopant atoms.
One prior art technique uses a p channel device on circuit inputs. This has the disadvantage of permitting an externally induced latch-up caused by a phenomenon known as "voltage bumping". If the input potential increases, or "bumps up", the structure of the p channel device results in a latchup. If the latchup consumes sufficient current, the device can destructively degenerate.
In providing ESD protection, it is desireable that a protective circuit not occupy significant surface area of the semiconductor die. It is further important that the protective circuit not cause significant time delays in the operation of the IC, or otherwise degrade the performance of the IC.